The present invention relates to a microcomputer system and, more particularly, to a microcomputer system wherein a master processor and at least one coprocessor are interconnected via a bus.
In a microprocessor fabricated on a single semiconductor chip, a very large number of circuit elements are required but the number of circuit elements capable of being formed in the single chip is limited. Therefore, it is difficult to fabricate such a unit in a single chip that executes high level instructions such as a floating-point arithmetic operations, a function arithmetic operations, etc., at a high speed. In order to solve this problem, a coprocessor is employed, which executes the high level instructions in place of the microprocessor. The coprocessor operates under the control of the microprocessor and is thus called a "slave processor". The microprocessor operates by itself as a central processing unit (CPU) to control the coprocessor along with a memory and peripheral units and is thus called a "master processor".
When the master processor decodes a high level instruction, it makes access to the slave processor to transfer the high level instruction as well as one or more operands, if necessary. The slave processor is thereby brought into an operative condition to execute the high level instruction thus supplied. If the master processor is not connected with a slave processor, it should execute the high level instructions by use of its own arithmetic unit. Therefore, the master processor is required to detect whether or not the slave processor is connected thereto. In a case where a slave processor is provided, moreover, if an arithmetic exception occurs in the arithmetic result or arithmetic procedure of the slave processor, the master processor should perform the processing operation for the arithmetic exception occurring in the slave processor. Therefore, the master processor is further required to detect whether or not the status information of the slave processor should be read.
For these purposes, the master processor includes first and second terminals supplied respectively with a busy signal and a status read request signal from the slave processor, as disclosed in the above copending application. When the master processor decodes and transfers the high level instruction to the slave processor, the slave processor changes the busy signal from an inactive level to an active level and holds the active level of the busy signal during the executing period thereof. When the slave processor completes the execution of the high level instruction, it changes the busy signal from the active level to the inactive level. At this time, if no arithmetic exception occurs, the slave processor produces an inactive level of the status read request signal when it changes the busy signal from the active level to the inactive level. In contrast, if the arithmetic exception occurs, the slave processor produces an active level of the status read request signal. On the other hand, the master processor detects the level of the first terminal, i.e. the level of the busy signal, and further detects the level of the status read request signal supplied to the second terminal when the busy signal is in the inactive level. Thus, if the slave processor is not connected, both the first and second terminals of the master processor, i.e. both the busy signal and status read request signal terminals, are maintained to the inactive level and the active level, respectively. On the other hand, in cases where the slave processor is connected and no arithmetic exception occurs, the status read request signal is in the inactive level when the busy signal is changed from the active level to the inactive level. As a result, the master processor can detect whether or not the slave processor is connected thereto and whether or not the arithmetic exception occurs in the slave processor.
The high level instructions to be executed by the slave processor are divided into two types: the first type of instructions are such that the execution result is required to be returned to the master processor and the second type of instructions are such that the execution result is not required to be returned to the master processor and is stored into, for example, a register of the slave processor. When the first type instruction is read from an instruction memory, the master processor must wait for the completion of the execution of this type of instruction by the slave processor. On the other hand, when the slave processor executes a second type high level instruction, the master processor can execute subsequent low level instructions in parallel to the execution of the second type high level instruction by the slave processor.
Although the master processor does not require the execution result of the second type high level instruction, it should detect whether or not the arithmetic exception occurs in the slave processor and, if it occurs, read the status information to detect the kind of arithmetic exception. To this end, the master processor always detects the levels at the first and second terminals, i.e. the levels of the busy signal and the status read request signal, after transferring the high level instruction, irrespective of the type of the high level instruction which is now to be executed by the slave processor. When the slave processor receives a new high level instruction, if the arithmetic exception has occurred in the execution result or the executing procedure of the preceding second type instruction, the slave processor changes the busy signal to the active level and immediately returns it to the inactive level, holding the status read request signal at the active level. In a case where the arithmetic exception has not occurred, the slave processor changes the busy signal to the active level and after changing the status read request signal to the inactive level, returns the busy signal to the inactive level. Thus, the master processor can detect whether or not the arithmetic exception has occurred in the execution of the second type high level instruction by the slave processor. However, since the master processor detects the levels of the first and second terminals whenever the high level instruction is decoded, execution of subsequent low level instructions is delayed when a new second type high level instruction is decoded and when the arithmetic exception has not occurred in the execution of the preceding second type high level instruction.